AMD begins production ramp of 256-core EPYC Venice — first 2nm HPC chip claims 70% performance leap
AMD has started the production ramp of its 6th Gen EPYC processor, Venice, which is the first high-performance computing chip to utilize TSMC's 2nm process technology. The Venice chip features up to 256 cores and claims a 70% performance improvement over its predecessor. AMD also plans to produce a follow-on processor called Verano and expand production to its facility in Arizona.
- ▪AMD's Venice processor is the first HPC product to reach production on TSMC's 2nm process technology.
- ▪The chip boasts up to 256 Zen 6 cores and a 70% performance gain over the EPYC Turin lineup.
- ▪AMD currently holds a 46% share of the server CPU revenue market as of Q1 2026.
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| Original publisher | Tom's Hardware |
| Canonical URL | https://www.tomshardware.com/tech-industry/semiconductors/amd-begins-production-ramp-of-256-core-epyc-venice-on-tsmcs-2nm-node |
| Publication time | Thu, 21 May 2026 12:12:15 +0000 |
| Retrieval time | 2026-05-21T12:16:11.034Z |
| Last seen | 2026-05-21T12:16:11.034Z |
| Headline source | Publisher (no WeSearch rewrite) |
| Excerpt source | publisher body |
| Excerpt method | First ~120 words (~800 chars) of extracted publisher body, fair-use limited. |
| Summary | WeSearch · cerebras-chat (WeSearch summarizer) |
| Summary source text | contentText |
| Citation coverage | Summary is a WeSearch-generated derivative; primary citation is the original publisher URL. |
| Cluster | YdTHsFSGV6oy · 2 stories |
| Cluster logic | Grouped by semantic title/content similarity across sources within a rolling window. Same-publisher template collisions are excluded from coverage comparison. |
| Ranking reason | Story pages are not engagement-ranked. Hub feeds use recency, with optional source-diversified chronological ordering (cap consecutive stories per source). No personalized ranking. |
| Publisher visit | Yes — open original |
| Substitutes article? | No — link-out required for full text |
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| Indexing | May the item be indexed (stored, ranked, made findable)? | Allowed |
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| AI summary | May WeSearch generate its own short summary of the article? | Limited |
| Retrieval / RAG | May the content be exposed for third-party retrieval-augmented generation? | Not asserted |
| Model training | May the content be used to train AI models? | Not asserted |
| Commercial reuse | May the content be reused commercially? | Not permitted |
Basis: Derived from the published RSS/Atom feed. Contact: [email protected]. Reviewed: 2026-07-24.
Opening excerpt (first ~120 words) tap to expand
Tech Industry Manufacturing Semiconductors AMD begins production ramp of 256-core EPYC Venice — first 2nm HPC chip claims 70% performance leap News By Luke James published 21 May 2026 Intel's competing P-core Xeon won't arrive until 2027 at the earliest. When you purchase through links on our site, we may earn an affiliate commission. Here’s how it works. (Image credit: AMD) Copy link Facebook X Whatsapp Reddit Pinterest Flipboard Email Share this article 0 Join the conversation Follow us Add us as a preferred source on Google Newsletter Subscribe to our newsletter AMD has announced that its 6th Gen EPYC processor, codenamed Venice, has entered production ramp on TSMC's N2 (2nm-class) process technology in Taiwan.
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