AMD Spills Details on Next-Gen Epyc CPUs
However, the distribution of those cores and the internal chip layout were not confirmed, nor were other details of what these chips can do. Now we have it all.AMD is splitting Zen 6 Epyc into four classes: Venice SP7, Venice SP8, Venice-X, and Verano. These are all high-powered Zen 6 CPUs, but they offer different core count configurations and power limits, targeting different enterprise customers.
- ▪However, the distribution of those cores and the internal chip layout were not confirmed, nor were other details of what these chips can do.
- ▪Now we have it all.AMD is splitting Zen 6 Epyc into four classes: Venice SP7, Venice SP8, Venice-X, and Verano.
- ▪These are all high-powered Zen 6 CPUs, but they offer different core count configurations and power limits, targeting different enterprise customers.
PCMag files mainly under tech. We currently carry 371 of its stories.
Story provenance
Source · retrieval · rights · ranking — open for full record
inspect →
Story provenance
Attribution is not the same as permission. This drawer separates discovery metadata, excerpts, WeSearch-generated summaries, reuse status, and whether the publisher receives the visit. Nothing here claims a legal grant the publisher has not made.
Record
| Original publisher | PCMag |
| Canonical URL | https://www.pcmag.com/news/amd-spills-details-on-next-gen-epyc-cpus |
| Publication time | Fri, 24 Jul 26 16:48:42 +0000 |
| Retrieval time | 2026-07-24T17:04:14.025Z |
| Last seen | 2026-07-24T17:04:14.025Z |
| Headline source | Publisher (no WeSearch rewrite) |
| Excerpt source | publisher body |
| Excerpt method | First ~120 words (~800 chars) of extracted publisher body, fair-use limited. |
| Summary | WeSearch · cerebras-chat (WeSearch summarizer) |
| Summary source text | contentText |
| Citation coverage | Summary is a WeSearch-generated derivative; primary citation is the original publisher URL. |
| Cluster | -LCz-1UxMu8o |
| Cluster logic | Grouped by semantic title/content similarity across sources within a rolling window. Same-publisher template collisions are excluded from coverage comparison. |
| Ranking reason | Story pages are not engagement-ranked. Hub feeds use recency, with optional source-diversified chronological ordering (cap consecutive stories per source). No personalized ranking. |
| Publisher visit | Yes — open original |
| Substitutes article? | No — link-out required for full text |
Rights status (four layers)
WeSearch handling by dimension
| Indexing | May the item be indexed (stored, ranked, made findable)? | Allowed |
| Snippet | May a short excerpt of the publisher's text be shown? | Allowed |
| AI summary | May WeSearch generate its own short summary of the article? | Limited |
| Retrieval / RAG | May the content be exposed for third-party retrieval-augmented generation? | Not asserted |
| Model training | May the content be used to train AI models? | Not asserted |
| Commercial reuse | May the content be reused commercially? | Not permitted |
Basis: Derived from the published RSS/Atom feed. Contact: [email protected]. Reviewed: 2026-07-24.
Opening excerpt (first ~120 words) tap to expand
AMD CEO Lisa Su officially unveiled the company's next-generation Epyc CPUs at the Advancing AI 2026 event in San Francisco on Thursday, including details on the core layout, the new socket designs, memory support, feature sets, and more.AMD previously confirmed that Epyc Venice CPUs would have up to 256 cores, leveraging its high-core-density Zen 6c variant. However, the distribution of those cores and the internal chip layout were not confirmed, nor were other details of what these chips can do. Now we have it all.AMD is splitting Zen 6 Epyc into four classes: Venice SP7, Venice SP8, Venice-X, and Verano. These are all high-powered Zen 6 CPUs, but they offer different core count configurations and power limits, targeting different enterprise customers.
…
Excerpt limited to ~120 words for fair-use compliance. The full article is at PCMag.
Discussion
0 commentsMore from PCMag
