Fault tolerance estimation in digital circuits with visualised generative networks
A new numerical method for estimating fault tolerance in digital circuits has been proposed. This method utilizes a generative network sampling technique to analyze failure modes in circuit structures. The study aims to enhance the robustness of electronic designs by evaluating the impact of various error modes on logical elements.
- ▪The proposed method compares expected output currents to realistic signals from numerical experiments.
- ▪It focuses on analyzing the deviation from ideal digital electronic signals caused by different failure modes.
- ▪The research involves a representation of the Generative Adversarial Network in terms of complex variables.
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| Original publisher | arXiv cs.AI |
| Canonical URL | https://arxiv.org/abs/2605.15212 |
| Publication time | Mon, 18 May 2026 00:00:00 -0400 |
| Retrieval time | 2026-05-18T04:04:54.418Z |
| Last seen | 2026-05-18T04:04:54.418Z |
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| Summary source text | contentText |
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| Commercial reuse | May the content be reused commercially? | Not permitted |
Basis: Derived from the published RSS/Atom feed. Contact: [email protected]. Reviewed: 2026-07-24.
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Computer Science > Hardware Architecture arXiv:2605.15212 (cs) [Submitted on 9 May 2026] Title:Fault tolerance estimation in digital circuits with visualised generative networks Authors:Sascha Biel, Carl Alexander Gaede, Amiel Glaser, Jan Wolter, Alexej Schelle View a PDF of the paper titled Fault tolerance estimation in digital circuits with visualised generative networks, by Sascha Biel and 4 other authors View PDF HTML (experimental) Abstract:We propose a new numerical method to estimate the fault tolerance of failure modes in digital circuit structures with a generative network sampling technique.
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