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FusionCell: Cross-Attentive Fusion of Layout Geometry and Netlist Topology for Standard-Cell Performance Prediction

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FusionCell: Cross-Attentive Fusion of Layout Geometry and Netlist Topology for Standard-Cell Performance Prediction
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The article introduces FusionCell, a new dual-modality predictor for standard-cell performance prediction. It integrates layout geometry and netlist topology to enhance accuracy and speed in performance characterization. Experimental results show significant improvements in prediction error and characterization time compared to traditional methods.

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Record

Original publisherarXiv cs.AI
Canonical URLhttps://arxiv.org/abs/2605.20287
Publication timeFri, 22 May 2026 00:00:00 -0400
Retrieval time2026-05-22T04:02:00.009Z
Last seen2026-05-22T04:02:00.009Z
Headline sourcePublisher (no WeSearch rewrite)
Excerpt sourcepublisher body
Excerpt methodFirst ~120 words (~800 chars) of extracted publisher body, fair-use limited.
SummaryWeSearch · cerebras-chat (WeSearch summarizer)
Summary source textcontentText
Citation coverageSummary is a WeSearch-generated derivative; primary citation is the original publisher URL.
Cluster-YR0kTopuqxx
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Ranking reasonStory pages are not engagement-ranked. Hub feeds use recency, with optional source-diversified chronological ordering (cap consecutive stories per source). No personalized ranking.
Publisher visitYes — open original
Substitutes article?No — link-out required for full text

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Basis: Derived from the published RSS/Atom feed. Contact: [email protected]. Reviewed: 2026-07-24.

Opening excerpt (first ~120 words) tap to expand

Computer Science > Machine Learning arXiv:2605.20287 (cs) [Submitted on 19 May 2026] Title:FusionCell: Cross-Attentive Fusion of Layout Geometry and Netlist Topology for Standard-Cell Performance Prediction Authors:Haoyi Zhang, Kairong Guo, Bojie Zhang, Yibo Lin, Runsheng Wang View a PDF of the paper titled FusionCell: Cross-Attentive Fusion of Layout Geometry and Netlist Topology for Standard-Cell Performance Prediction, by Haoyi Zhang and 4 other authors View PDF HTML (experimental) Abstract:Standard cells form the building blocks of digital circuits, so their delay and power critically influence chip-level performance; yet characterization still relies on slow simulation sweeps, and many fast predictors ignore layout geometry, missing coupling and layout-dependent effects.

Excerpt limited to ~120 words for fair-use compliance. The full article is at arXiv cs.AI.

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