Show HN: FpgacapZero on BRS-100-GW1NR9 dev board
The BRS-100-GW1NR9 FPGA development board now supports fpgacapZero, an open-source FPGA debug core. This integration allows users to utilize an Embedded Logic Analyzer and I/O block without vendor-specific tools. The setup process is streamlined, requiring only a single build flag to enable the ELA core in the bitstream.
- ▪fpgacapZero provides an open-source, vendor-agnostic debugging solution for FPGA development.
- ▪The integration process involved configuring JTAG connections and creating a specific GoWIN JTAG TAP module.
- ▪Users can easily enable the ELA core by following a simple command sequence after cloning the repository.
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| Original publisher | Hackster.io |
| Canonical URL | https://www.hackster.io/brisbanesilicon/supporting-fpgacapzero-on-the-brs-100-gw1nr9-442d56 |
| Publication time | Wed, 20 May 2026 04:50:21 +0000 |
| Retrieval time | 2026-05-20T05:04:59.770Z |
| Last seen | 2026-05-20T05:04:59.770Z |
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Opening excerpt (first ~120 words) tap to expand
Bringing fpgacapZero to the BRS-100-GW1NR9We've all been there. The sim looks perfect, the bitstream loads first try, and then the board just... sits there, doing something weird and refusing to explain itself. At that point you either reach for a vendor debug tool and accept being chained to their IDE, or you start sprinkling LEDs across your design like breadcrumbs.Neither is much fun.So we're stoked to announce that our BRS-100-GW1NR9 FPGA development board now has out-of-the-box support for fpgacapZero — an open-source, vendor-agnostic FPGA debug core by Leonardo Capossio. If you haven't come across it before, fpgacapZero (or just "fcapZ") drops a tidy little Embedded Logic Analyzer and Embedded I/O block straight into your fabric, and lets you poke at it over JTAG via OpenOCD.
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